1. Field of the Invention
The present invention relates in general to the field of information processing, and more specifically to a signal processing system and method for reducing comparators in delta sigma modulator, analog-to-digital comparators using quantizer output prediction.
2. Description of the Related Art
Many signal processing systems include delta sigma modulators to quantize an input signal into one or more bits. Delta sigma modulators trade-off increased noise in the form of quantization error in exchange for high sample rates and noise shaping. “Delta-sigma modulators” are also commonly referred to using other interchangeable terms such as “sigma-delta modulators”, “delta-sigma converters”, “sigma delta converters”, and “noise shapers”.
FIG. 1 depicts an analog-to-digital converter (ADC) delta sigma modulator 100 that receives an analog input signal x(t) and converts the input signal x(t) into a series of low resolution, digital output pulses q(n), where t represents a continuous time variable and n denotes a discrete time variable. The average amplitude over time of the series of low resolution pulses is q(n). In general, the delta sigma modulator 100 quantizes a difference between the current input signal x(t) and an analog version of the previous quantizer output signal, i.e. q(t−1). In the feedback loop of delta sigma modulator 100, a digital-to-analog converter (DAC) 108 converts each delayed (z−1) output signal q(n−1) into an analog signal q(t−1). The feedback loop of delta sigma modulator 100 also includes dynamic element matching 106 to correct nonlinearities in the DAC 108 signal q(n−1).
The noise shaping loop filter 102 processes a difference between input signal x(t) and the delayed output signal q(t−1) to generate a loop filter output signal/quantizer input signal VLF. During each output cycle of delta sigma modulator operation, quantizer 104 quantizes signal VLF to generate output signal q(n), generally in the form of digital data. When loop filter 102 is a continuous time filter, the quantizer 104 represents a relatively low-accuracy ADC converter operating at an oversampling rate, such as a rate of 64:1. Quantizer 104 can provide multi-bit or one-bit output quantization levels. The quantization level step size, Δ, represents the difference between each quantization level. One-bit quantizers have only two quantization levels specified as {−α/2, α/2} or {−1,1}. Shreier and Temes, Understanding Delta-Sigma Signal Converters, IEEE Press, 2005 (referred to herein as “Shreier & Temes”) describes conventional delta-sigma modulators in more detail.
Multi-bit ADC delta sigma modulators exhibit some well-known advantages over single bit ADC delta sigma modulators such as reduced quantization noise. However, quantizer design continues to represent one of the significant challenges confronting delta sigma modulator designers.
FIG. 2 depicts a flash-type quantizer 200, which represents one embodiment of quantizer 104. Quantizer 200 includes r comparators 202.0-202.r−1, each having a first input connected to the output of loop filter 102 to receive quantizer input signal VLF. “r” is a positive integer representing the number of comparators in delta sigma modulator 100. Each of the comparators 202.0-202.r−1 includes a second input to receive respective reference voltages V0 through Vr−1. The reference voltages serve as reference signals to quantize the quantizer input signal VLF. A resistor string reference ladder of r−1 resistors 204.1-204.r−1 of value R generates uniform voltage drops across at least reference resistors 204.1-204.r−1 to generate respective reference voltages V0 through Vr−1. The end resistors 204.0 and 204.r have values that can be used to scale the quantization levels (also referred to as a “quantizer step”). For example, the largest quantizer threshold may be 1.2 V, but the available reference may be 2.5 V, so resistors 204.0 and 204.r are set to achieve the desired scale. A reference voltage of +Vref to −Vref is applied across the reference resistors 204.0-204.r. +/−Vref is, for example, +/−1.5 Volts (V).
Each of comparators 202.0-202.r−1 compares the quantizer input signal VLF with respective reference voltages V0 through Vr−1. The ith comparator 202.i generates a logical zero (e.g. 0 V) when the ith reference voltage Vi is less than or equal to the loop filter output/quantizer input signal VLF and a logical one (e.g. +2.5 V) when Vi>VLF. Once during each cycle of quantizer 104 operation, digital encoder 206 encodes the output signals of comparators 202.0-202.r−1 into a digital (discrete) output signal q(n).
Increasing the number of comparators in quantizer 104, i.e. increasing the value of r, yields a higher quality output signal q(n) (e.g. less quantization noise) and higher signal bandwidth capabilities. Each time r doubles, delta sigma modulator 100 typically achieves a 6 dB quantization noise improvement. However, disadvantages also accompany increasing the number of comparators in quantizer 104. For example, increasing the number of comparators requires more physical area to implement and more power to operate. Additionally, increasing the number of comparators decreases voltage spacing between adjacent reference voltages Vi and Vi+1 and increases the relative effects of non-idealities, such as comparator offset voltages.
Comparator offset voltages represent the minimum direct current (DC) input voltage that would have to be applied to input terminals of the comparator to cause the comparator to transition state. Thus, comparator offset voltages can cause error in the comparator outputs, especially when the difference between the reference input signals of adjacent comparators is small. Accordingly, as the relative effects of quantizer non-idealities increase, the nonidealities cause increasing delta sigma modulator error. The non-linearity can cause harmonic distortion, especially at high signal frequencies, increased noise, and modulation of noise with the direct current (DC) input level, all of which are undesirable.
An example with the number of comparators equal to r=16 illustrates effects of comparator nonidealities. Assuming seventeen (17) quantization levels, normalized to −8, −7, −6, . . . , −1, 0, +1, +2, . . . , +8, the input reference voltages V0 through V15 to respective comparators 202.0-202.r−1 are normalized values of −7.5, −6.5, −5.5, . . . , −0.5, +0.5, . . . , +5.5, +6.5, +7.5. Each actual reference voltage Vi scales with the analog system reference voltage Vref. For example, if level −8 corresponds to −1.5 V and level +8 corresponds to +1.5 V, then the respective comparator input voltage references V0 through V15 for comparators 202.0-202.r−1 are −7.5/8*1.5, −6.5/8*1.5, . . . , +6.5/8*1.5, and +7.5/8*1.5V. Thus, as the number of comparators increases the voltage reference spacing decreases. It follows that as the number of comparators increases, eventually non-linearities of the flash-type quantizer 200 counteract any advantage obtained by increasing the number of comparators. Additionally, in an integrated circuit, chip area is valuable. Increasing the number of comparators requires more chip area and, thus, can become a dominant disadvantage.
FIG. 3 depicts a tracking ADC quantizer 300, which represents another embodiment of quantizer 104. The tracking ADC quantizer 300 is described in detail in Dorrer et al., A 3-mW 74-dB SNR 2-MHz Continuous-Time Delta-Sigma ADC With a Tracking ADC Quantizer in 0.13-μm CMOS, IEEE Journal of Solid-State Circuits, Vol. 40, No. 12, December 2005. The quantizer 300 reduces the number of comparators to three comparators 302.0, 302.1, and 302.2, a counter 304, an R-string reference ladder 306, and a switching matrix 308 to connect the reference voltages V0, V1, and V2 to the inputs of comparators 302.0, 302.1, and 302.2. When the loop filter 102 output voltage VLF has a value of 1 least significant bit (LSB) or less, only the middle comparator 302.1 will change state, and the state of counter 304 remains unchanged. For VLF signal changes larger than 1 LSB, adjacent comparators 302.2 or 302.0 will change state depending upon whether the change is greater than or less than the previous state. The logic 310 detects this state change and increases the output of counter 304 or decreases the output of counter 304 depending upon whether comparator 302.2 or 302.0 changed state. By changing the state of counter 304, the reference voltages V0, V1, and V2 to respective comparators 302.0, 302.1, and 302.2 are tracked to the new output value of counter 304. In each cycle of operation of delta sigma modulator 300, the output signal q(n) of quantizer 300 is generated by using the result of counter 304 and the output signal of comparators 302.0, 302.1, and 302.2.
Despite developments in quantizer technology, ADC delta sigma modulator quantizer design can still be improved to reduce the number of comparators used in comparable ADC delta sigma modulator quantizer designs and the effects of comparator non-idealities.